Managing memory and memory cache units is a critical aspect of the design, development and testing of multiple processor computer systems, particularly with the growing number of processors and system buses implemented in existing and planned scalable symmetric multiple processor systems. The coherency of cache memories utilized by each of the processors and the system as a whole is a critical performance and accuracy issue.
Several approaches have been taken in the prior art in attempting to evaluate cache coherency. Two of the more prominent are formal verification and system-wide simulation based evaluation.
Formal verification involves the creation of mathematical models to represent the cache coherency protocol. Formal verification becomes very complex as the coherency scheme scales up and becomes complex itself. It is in fact quite difficult, if not impossible, to apply formal verification to modern, highly scaled and complex symmetric multiprocessing systems. Additionally, formal verification can not be applied during production for final product testing and evaluation.
System-wide simulation based evaluation requires detailed cycle by cycle timing of events across an entire system. Coherency schemes often involve complicated rules which govern the ownership of a given global cache line. Adding to the complexity is the phased nature of modern processor buses. It becomes very tricky to track the phase of every transaction on every bus in the entire symmetric multiprocessing system. Systems can have 10 or more buses and 16 or more processors with outstanding transactions. The intrinsic complexity of this approach prohibits its use during production or final product testing and evaluation as in the formal verification approach.
What is needed is a computationally efficient method and system for implementing and evaluating scalable symmetric multiple processor cache coherency protocols and algorithms.